Digital memory circuit with several memory banks has first read/write data line bundle associated with first/second halves of first/second banks, second bundle with remaining halves

摘要

The circuit has at least two pairs of adjacent banks, a bundle of input/output lines, a controller and a changeover device. Only two bundles of read/write data lines are provided per pair of adjacent memory banks, the first associated with the first and second halves of the first and second banks and the second with the second and first halves of the first and second banks. The circuit has at least two pairs of adjacent banks (BK00-BK11), each with a number of memory cells in each bank, a bundle of input/output lines, a controller (120) and a changeover device (30) controllable depending on a clock signal for connecting the input/outputs lines to the first and second halves of the addressed memory bank during first and second half periods. Only two bundles (LDa,b) of read/write data lines are provided per pair of adjacent memory banks, the first associated with the first and second halves of the first and second banks and the second with the second and first halves of the first and second banks.