TESTING OF CIRCUIT WITH PLURAL CLOCK DOMAINS

摘要

An electronic circuit has a plurality of sub-circuits (12a,12b) .Clock gate circuits (14a,14b) supply gated clock signals (GCLK1, GCLK2) to data storage elements (120,122) of the sub-circuits. The clock gate circuits have gate inputs (148) for receiving gate signals (STOP) that commands blocking passage of the clock signal. Data can be transferred between data storage elements between two of the sub circuits. A detector circuit (16) flags invalid data in the data storage element (122) of the second one of the sub-circuits (12b) .The detector circuit has a flag storage element (32) arranged to set a flag when the clock gate circuit (14b) of the second one of the sub-circuits (12b) passes the clock signal for the second one of the sub-circuits after the clock gate of the first one of the sub-circuits has blocked the clock signal for the first one (12a) of the sub-circuits. The flag indicates the relative phase of the clocks signals of different sub-circuits when the clocks are stopped. The flag is used to invalidate data in the data storage element of the second one of the sub-circuits (12b) .