摘要 |
An apparatus and method for generating a cyclic redundancy code with multiple cyclic redundancy code circuits are disclosed. High throughput data protocols can work more robustly if accompanied by high throughput error checking to verify the integrity of the communicated data. One approach of improving the performance of cyclic redundancy code generation hardware that can save money and development time is to combine multiple cyclic redundancy code circuits to perform the error checking. Data received is processed across the multiple cyclic redundancy code circuits. Future cyclic redundancy code circuits can also be combined according to this approach. |