| 摘要 |
A demultiplexer apparatus has a plurality of integrating circuits which operate in parallel. The plurality of integrating circuits receive in parallel an input time-series binary data. One of the plurality of integrating circuits in a current stage converts the input binary data into multi-value data in the current stage, and generates recovery data in the current stage based on the multi-value data and recovery data from one of the plurality of integrating circuits in a stage immediately or more previous to the current stage integrating circuit. The plurality of integrating circuits output the generated recovery data as parallel data to the input binary data. In this way, the demultiplexer apparatus which can read the input binary data with a frequency component exceeding a maximum operation frequency is provided. <IMAGE>
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