| 摘要 |
A Fast Hadamard Transform apparatus has a plurality of transform stages (0,1,2...), such as would be employed by a wireless telecommunication system for detecting and correcting errors that occur during the transmission of coded signal blocks, such as a Walsh codeword. Each stage of the apparatus comprises an adder (106) and a subtractor (108), each having an output terminal. The adder and the subtractor are configured to receive signal pairs and generate intermediate coefficients. A first memory unit (116) is coupled to the output terminal of the adder and to the output terminal of the subtractor, and is configured to receive a first specifiable sequence of the intermediate coefficients from the adder and a second specifiable sequence of the intermediate coefficients from the subtractor. A second memory unit (118) is coupled to the output terminal of the subtractor so as to receive a third specifiable sequence of the intermediate coefficients from the subtractor. The first memory unit and the adder provide concurrently a plurality of intermediate coefficient signal pairs to a subsequent transform stage, and the first and second memory units provide concurrently a plurality of other intermediate coefficient signal pairs to the subsequent transform stage <IMAGE> |
