FeRam capacitor stack etch

摘要

The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer (126) with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask (299). Alternatively, the PZT ferroelectric layer is etched using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a "shorting out" of the resulting FeRAM capacitor. <IMAGE>