| 摘要 |
A phase detector capable of operating at a half rate in a half-rate clock and data recovery (CDR) circuit includes a first latch circuit which receives an input signal, an inverted input signal and a half-rate clock, a second latch circuit which receives a first output signal and an inverted first output signal from the first latch circuit and an inverted half-rate clock, a further first latch circuit which receives the input signal, the inverted input signal and the inverted half-rate clock, a further second latch circuit which receives a further first output signal and an inverted further first output signal form the further first latch circuit and the half-rate clock, a selector circuit which receives the first output signal and the inverted first output signal and the further first output signal and the inverted further first output signal, the half-rate clock and the inverted half-rate clock so as to output a retimed signal and an inverted retimed signal and an exclusive OR circuit which receives a second output signal and an inverted second output signal from the second latch circuit and a further second output signal and an inverted further second output signal from the further second latch circuit so as to output a reference signal and an inverted reference signal.
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