发明名称 CIRCUIT AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a circuit and a method for testing a semiconductor integrated circuit, which can easily test a limitation of an operation cycle, i.e., a delay characteristic of the semiconductor integrated circuit device at an arbitrary cycle in a function test pattern of the semiconductor integrated circuit, by using the function test pattern and a relatively slow clock signal input from the outside. SOLUTION: The test circuit includes a one-shot circuit which generates a prescribed one-shot signal from a clock signal input from the outside by using a first delay adjusting signal, a variable delay circuit which delays an output signal from the one-shot circuit for a prescribed period by using a second delay adjusting signal, a NAND circuit which inverts an output signal from the variable delay circuit and outputs it, and an AND circuit which products an AND signal of an output signal from the NAND circuit and the clock signal input from the outside. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003215205(A) 申请公布日期 2003.07.30
申请号 JP20020011985 申请日期 2002.01.21
申请人 NEC CORP 发明人 YAMANOBUTA HISASHI
分类号 G01R31/28;G01R31/3183;G01R31/319;H01L21/822;H01L27/04;(IPC1-7):G01R31/28;G01R31/318 主分类号 G01R31/28
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