| 摘要 |
PROBLEM TO BE SOLVED: To enable batch stress applying for all ferroelectric memory capacitors 3, 4 and to realize shortening of a test time in a ferroelectric memory device in which tests of applying positive electric field and negative electric field to ferroelectric memory capacitors 3, 4 alternately are performed. SOLUTION: A transistor 8 for bit line applying is provided at each end part of bit lines BIT<SB>0</SB>-BITM, BIT<SB>0</SB>B-BITMB, a bit line applying signal ALLBIT is simultaneously inputted to all bit lines BIT<SB>0</SB>-BITM, BIT<SB>0</SB>B-BITMB, while a transistor 9 for word line applying is provided at each end part of word lines WL<SB>0</SB>-WLN, a word line applying signal ALLWL is simultaneously inputted to all word lines WL<SB>0</SB>-WLN, further, an AND circuit 7a is provided at each end part of cell plate lines CP<SB>0</SB>-CPN, the cell plate lines CP<SB>0</SB>-CPN are driven linking with drive of word lines WL<SB>0</SB>-WLN. COPYRIGHT: (C)2003,JPO
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