| 摘要 |
In a circuit block BL1, a PMOS transistor P1 and a PMOS transistor P1' are connected in a series between a high-level potential HL and an output terminal U1; an NMOS transister N1 and an NMOS transistor N1' are connected in series between a low-level potential LL and the output terminal U1. An inversion signal Ck1B of a clock signal Ck1 is inputted to the gate of the PMOS transistor P1; the inversion signal Ck1B of the clock signal Ck1 is inputted to the gate of the PMOS transistor P1' through an inverter IV1; a clock signal Ck2 is inputted to the gate of the NMOS transistor N1; and the clock signal Ck2 is inputted to the gate of the NMOS transister N1' through an inverter IV2.
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