| 摘要 |
<p>A memory system comprises nonvolatile memory chips (CHP1, CHP2) having memory banks (BNK1, BNK2) capable of performing memory operations independently and a memory controller (5) capable of accessing/controlling separately the nonvolatile memory chips. The memory controller can selectively instruct the memory banks of the nonvolatile memory chips to perform a simultaneous or interleave write operation. Therefore, the simultaneous write operations each requiring a write time much longer than the write set-up time can be completely parallel carried out, and the interleave write operations following the write set-up can be carried out parallel and overlapped with a write operation of another memory bank. As a result, the number of nonvolatile memory chips constituting a memory system capable of performing a high-speed write operation can be relatively small.</p> |
