发明名称 BUS ARCHITECTURE AND COMMUNICATION PROTOCOL
摘要 A bus architecture wherein a plurality of devices are connected in a continuous loop. The devices included at least one master device (M-Bus Master 1, 2, n) and at least one slave device (M-Bus Slave 1, 2, n), the plurality of devices being directly connected to the continuous loop. Data is propagated through the devices from a source device to a destination device, terminates at the destination device, and can be sent out over a plurality of signal lines (Mdatain and Mdataout).
申请公布号 WO03060733(A1) 申请公布日期 2003.07.24
申请号 WO2002US01327 申请日期 2002.01.15
申请人 NANO STORAGE PTE LTD;WEST, GLENN, S.;BHASKARAN, SREEDHARAN;LAU, HOCK, LUB, JAMES 发明人 WEST, GLENN, S.;BHASKARAN, SREEDHARAN;LAU, HOCK, LUB, JAMES
分类号 G06F13/42;H04L12/40;(IPC1-7):G06F13/14;H04L12/28 主分类号 G06F13/42
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