SEMICONDUCTOR MEMORY SYSTEM HAVING A DATA CLOCK SYSTEM FOR RELIABLE HIGH-SPEED DATA TRANSFERS

摘要

A data clock system for a semiconductor memory system is provided for performing reliable high-speed data transfers. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths, each first data path in operative communication with a second data path. The data clock system includes a first clock path receiving a clock signal during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; and a second clock path receiving the clock signal from the first clock path and propagating the clock signal along therethrough, the second clock path including at least one clock driver. The transfer of data between the one of the plurality of first data paths and the second data path occurs upon receipt of the clock signal by the at least one clock driver. A method for propagating a clock signal in a semiconductor memory system is also provided for performing reliable high-speed data transfers. The semiconductor memory includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths. The method includes the steps of receiving a clock signal in a first clock path during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; receiving the clock signal in a second clock path; propagating the clock signal along the second clock path via at least one clock driver; and transferring the data between one of the first data paths and the second data path upon receipt of the clock signal by the at least one clock driver. In the inventive system and method the clock signal is delayed during propagation along the first clock path and the second clock path by approximately the same amount of time regardless if the at least one clock driver is positioned proximate a far end of the second clock path or the at least one clock driver is positioned proximate a near end of the second clock path.