| 摘要 |
A semiconductor integrated circuit having a latch including a data input terminal and a timing input terminal, has a first input terminal connected to the latch data input terminal and a second input terminal connected to the latch timing input terminal. A delay circuit, connected between the first and second input terminals, receives a test signal being supplied to a selected one of the first and second input terminals and supplies a delayed test signal to the nonselected one of the first and second input terminals.
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