| 摘要 |
A memory controller has separate memory controller agents that process memory transactions in parallel. A memory controller in accordance with the present invention includes a plurality of memory controller agents, which are coupled to each other via a series of busses, an incoming memory transaction dispatch unit, and an outgoing memory dispatch unit. Memory transactions are received from cacheable entities of a computer system at the incoming memory transaction dispatch unit, and are then presented to the plurality of agents. For each incoming transaction, one of the agents will accept the transaction. Each agent is responsible for ensuring coherency and fulfilling memory transactions for a single memory line. If multiple memory read transactions are received for a single memory line, the agents will configure themselves into a linked list to queue up the requests. The coherency information and memory line data associated with each memory line may be cached by each agent, thereby allowing repeated requests to the same memory line to be serviced more quickly. When two or more agents are queued up to fulfill multiple memory read transactions to the same memory line, the agents cooperate by transferring the coherency information and memory line data associated with each memory line from agent to agent, thereby minimizing the need to access main memory. The agents complete memory transactions back to the cacheable entities via the outgoing memory dispatch unit.
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