| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL circuit which has a wide lock frequency range and reduced power consumption. <P>SOLUTION: An input signal (REFCLK) to become a reference signal is inputted to the phase comparator 1 of the PLL circuit. The output of the phase comparator 1 is applied through a charge pump 2 to an LPF 3. The output of the LPF 3 is outputted to a VCO 4 and further outputted to comparators 7 and 8. The comparators 7 and 8 are supplied with the output of the LPF 3 and the tap output voltage of a reference voltage generating circuit 6 and compare the output voltage of the LPF 3 with the tap output value of the reference voltage generating circuit 6. The comparison result is outputted to the VCO 4, and the suitable number of stages of elements comprising the VCO 4 is controlled. The output of the VCO 4 is fed back to the phase comparator 1 via a frequency divider 5. <P>COPYRIGHT: (C)2003,JPO |
