发明名称 TEST DEVICE FOR SEMICONDUCTOR MEMORY DEVICE, AND TEST METHOD
摘要 PROBLEM TO BE SOLVED: To provide a test device and a test method which can test simultaneously a plurality of memory devices of which performances such as pause capability or the like are different. SOLUTION: The device is provided with a connection section 22A connecting DUT such as a DRAM or the like, a driver circuit 21A giving a write-in signal to the connection section corresponding to a test pattern outputted from a test pattern generating device 1, a timer 24A setting a pause time of DUT and a read time, a determination circuit 23A connected to the connection section, determining a normal/defective condition of DUT based on a level of a read signal from DUT, and transmitting a discriminated result to a result processing circuit 3, and a plurality of test circuits 24A having a counter 25A controlling operation of the driver circuit and the determination circuit corresponding to the test pattern, and a plurality of DUTs connected to the connection section of each circuit are tested simultaneously. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003203495(A) 申请公布日期 2003.07.18
申请号 JP20020000279 申请日期 2002.01.07
申请人 MITSUBISHI ELECTRIC CORP 发明人 OCHI TAKEHIRO
分类号 G01R31/3183;G01R31/28;G11C29/56;(IPC1-7):G11C29/00;G01R31/318 主分类号 G01R31/3183
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