发明名称 |
Multi-mode reed-solomon decoder based upon the PGZ algorithm and associated method |
摘要 |
A multi-mode Reed-Solomon decoder is disclosed. According to the invention, by simplifying the Peterson-Gorenstein-Zierler (PGZ) algorithm the goal of correcting different numbers of errors (t<=3) using a single hardware architecture is achieved. Through optimization without requiring finite field inversion operations, the hardware and the computing efficiency are both improved. The invention also discloses a register transistor level (RTL) hardware architecture to applied in error control codes (ECC) between a processor and a memory and other high-speed communication systems.
|
申请公布号 |
US2003135810(A1) |
申请公布日期 |
2003.07.17 |
申请号 |
US20020302825 |
申请日期 |
2002.11.25 |
申请人 |
VIA TECHNOLOGIES, INC. |
发明人 |
HSU H.Y.;WANG S.F.;WU ANYEU;CHEN HOWEN |
分类号 |
H03M13/15;(IPC1-7):H03M13/00 |
主分类号 |
H03M13/15 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|