| 摘要 |
A novel bias voltage generating circuit (12) and method are disclosed. In one embodiment, the bias voltage generating circuit includes a first transistor (20) with a base terminal coupled to the output node and an emitter terminal coupled to ground. The circuit also includes a resistor (24) with a first terminal coupled to a supply voltage node (Vcc) and a second terminal coupled to a collector terminal of the first transistor (20). A second transistor (26) has an emitter terminal coupled to the collector terminal of the first transistor (20) and a base terminal connected to the collector terminal of the second transistor (26). A second resistance (28) has a first terminal coupled to the supply voltage node (Vcc) and a second terminal coupled to a collector terminal of the second transistor (26). A third transistor (30) has a base terminal coupled to the base terminal of the second transistor (26), a collector terminal coupled to the supply voltage node (Vcc), and an emitter terminal coupled to the output node (Verias). The bias voltage generating circuit (12) utilizes a larger portion of available supply voltage (Vcc) for sensing current than conventional emitter follower bias circuits, and is therefore much less sensitive to supply voltage changes than conventional bias circuits. |
