发明名称 Structural regularity extraction and floorplanning in datapath circuits using vectors
摘要 In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The functional regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the functional characteristics of a logic design. Some embodiments of the functional regularity extraction component automatically generate a set of templates to cover a circuit. A template is a representation of a subcircuit with at least two instances in the circuit. The templates generated by the functional regularity extraction component are used by a structural regularity extraction component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design. Some embodiments of the structural regularity extraction component automatically generate a set of vectors for the logic design. A vector is a group of template instances that are identical in function and in structure. The vectors generated by the structural regularity extraction component are used by a floorplanning component. The floorplanning component provides a method of generating a circuit layout from the set of vectors. In some embodiments, each vectors corresponds to a row in the circuit layout.
申请公布号 US6594808(B1) 申请公布日期 2003.07.15
申请号 US19990435112 申请日期 1999.11.05
申请人 INTEL CORPORATION 发明人 KALE SUDHAKAR;CHOWDHARY AMIT;SARIPELLA PHANI;SEHGAL NARESH K.;GUPTA RAJESH
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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