| 摘要 |
PROBLEM TO BE SOLVED: To provide a time division multiplex signal generating circuit by which a phase margin is not deteriorated in a test pattern to be outputted as a time division multiplex signal. SOLUTION: The time division multiplex signal generating circuit gives a plurality of parallel signals from a signal generating part 1 to a time division multiplexing circuit 4 and multiplexes them in response to a frequency division signal obtained by dividing the frequency of a clock signal. The circuit includes a phase synchronizing means 2 for progressing the phase of the clock signal and a frequency dividing means for dividing the output of the phase synchronizing means by prescribed number of clock and, then, multiplexes the parallel signals from the signal generating part 1 by time division by the output of the phase synchronizing means. COPYRIGHT: (C)2003,JPO
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