| 摘要 |
A delay circuit, comprising: a plurality of delay blocks connected in series, each having a first complementary input terminal to which a first complementary signal is inputted, a second complementary input terminal to which a second complementary signal is inputted, and a complementary output terminal which outputs a third complementary signal delaying by selecting one of the first and second complementary signals based on logic of a delay selection signal, the complementary output terminal of the delay blocks except for the delay block of last stage being connected to the second complementary input terminal of the subsequent delay block, respectively, a complementary delay signal delaying the first complementary signal in accordance with logic of the delay selection signal being outputted from the complementary output terminal of the delay block of last stage, and the same first complementary signal is inputted to the first complementary input terminals of the plurality of delay blocks, respectively.
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