| 摘要 |
A method of using low voltage-swing clocks (512) with CMOS latches (502-522, 504-524) and with bi-CMOS latches (904-914, 906-916) and associated circuit structures to reduce power requirements of these circuits compared to conventional CMOS and bi-CMOS circuits. Also, a method of using low voltage-swing clocks (1136) to control CMOS (FIG. 11) and bi-CMOS dynamic logic. The power consumption of CMOS and bi-CMOS microprocessors and other chips can be substantially reduced by using low voltage-swing clocks, with savings of up to 60% to 80% of the normal clock power at speeds comparable to using normal latches and dynamic logic gates, with noise margins sufficient for safe operation.
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