| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a frequency divider circuit in which the delay time of a clock signal is hardly changed even when the frequency dividing ratio of the inputted clock signal is changed. <P>SOLUTION: The frequency divider circuit has a frequency dividing means 1 for outputting a plurality of frequency divided clock signals by dividing the frequency of the input clock signal, a first selecting means 2 for selecting one of a plurality of frequency divided clock signals outputted from the frequency dividing means, a synchronizing means 3 for synchronizing the frequency divided clock signal selected by the first selecting means on the basis of the input clock signal, a delay means 4 for outputting a delayed clock signal by delaying the input clock signal for a prescribed period, and a second selecting means 5 for selecting one of the frequency divided clock signal outputted from the synchronizing means and the delayed clock signal outputted from the delay means. <P>COPYRIGHT: (C)2003,JPO |
