发明名称 System independent and scalable packet buffer management architecture for network processors
摘要 A circular buffer storing packets for processing by one or more network processors employs an empty buffer address register identifying where a next received packet should be stored, a next packet address register identifying the next packet to be processed, and a packet-processing address register within each network processor identifying the packet being processed by that network processor. The n-bit addresses to the buffer are mapped or masked from/to the m-bit packet-processing address registers by software, allowing the buffer size to be fully scalable. A dedicated packet retrieval instruction supported by the network processor(s) retrieves a new packet for processing using the next packet address register and copies that into the associated packet-processing address register for use in subsequent accesses. Buffer management is thus independent of the network processor architecture.
申请公布号 US2003123454(A1) 申请公布日期 2003.07.03
申请号 US20020290766 申请日期 2002.11.08
申请人 STMICROELECTRONICS, INC. 发明人 KARIM FARAYDON O.;CHANDRA RAMESH;STRAMM BERND H.
分类号 G06F12/02;H04L12/46;H04L12/56;(IPC1-7):H04L12/28 主分类号 G06F12/02
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