| 摘要 |
A synchronous memory device is capable of reducing the number of address pins by changing address input. The synchronous memory device includes at least one common pin receiving a first signal and a second signal, latch circuits coupled to the common pin, wherein the latch circuit latches the first and second signals and one of the latch circuits selectively outputs the first or second signal in response to first or second internal clock pulses, and a clock pulse generator for receiving an external clock signal and for producing the first and second internal clock pulses from the external clock signal.
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