| 摘要 |
A memory cell comprises a first and a second inverters (103a,103b) connected in a latch configuration. The inverters have respective first and second means (SP1,SN1,SP2,SN2) for receiving a first and a second voltage supplies (VDD,GND), respectively. The cell also comprises means (STa,STb), responsive to a memory cell selection signal (SEL), for selectively connecting an input of at least one of the first and second inverter to at least one respective input/output data line (I/O,I/ON), carrying an input datum to be written in the memory cell in a memory cell write operation and an output datum read from the memory cell in a memory cell read operation. For flash-clearing the memory cell, means (SWa,SWb) are provided for switching at least one of the first and second voltage supply receiving means of at least one of the first and second inverters between the first voltage supply and the second voltage supply. The memory cell is particularly adapted to implement a flash-clear function in a memory device. <IMAGE> |
