| 摘要 |
An architecture and process for forming CMOS vertical replacement gate transistors is disclosed. An integrated circuit structure includes a major surface with first (120) and second (114) doped regions separated by an isolation region (140) which may be of silicon dioxide. Layers are deposited over these regions with trenches (200,202, Fig. 24) formed therein. Doped regions of the opposite conductivity from the respective first (120) and second (114) doped regions are formed in the trenches to form the channels of MOSFETs, with oxide layers (226,227) separating the channels from gates (240,242), which may be of polysilicon. The structure may also include doped regions (250,252) lying directly above first (120) and second (114) doped regions, having the same conductivity type as their respective region below and acting as source/drain regions in the MOSFET. These regions may be formed by diffusion of dopants from doped layers (142,144,160,164) in proximity to these regions. A method of forming the structure is also disclosed, where a sacrificial layer (152, Fig. 29) is removed before forming the gates (240,242), and boron and phosphorous-doped TEOS layers (142,146, Fig.18) are used in forming doped regions. |
