Output buffer circuit

摘要

An output buffer circuit is provided for maintaining the slew rate of output waveforms of the output signal within a predetermined range regardless of changes of load on the output terminal. Series-connected feedback delay circuits (11-14) delay an input signal (IN) on the basis of the potential of an output signal (OUT) obtained through a feedback path (L1). Delay time of each feedback delay circuit varies according to load on an output terminal (2). Delay signals from the feedback delay circuits (11-14) are applied to one inputs of high-output selecting NAND gates (G11-G14), respectively. The NAND gates (G11-G14) also receive the input signal (IN) at their other inputs and output signals to gates of high output transistors (QP1-QP4), respectively. At the rise of the input signal (IN), the high output transistors (QP1-QP4) output the output signal (OUT) in response to the delay signals from the feedback delay circuits (11-14).