发明名称 High-speed compound semiconductor device having a minimized parasitic capacitance and resistance
摘要 A method of fabricating a semiconductor device includes the steps of forming an insulation film on a compound semiconductor layer, forming an opening in the insulation film so as to expose a part of the compound semiconductor layer, forming a gate electrode of a refractory metal compound on the insulation film such that the gate electrode contacts with the compound semiconductor layer at the contact hole, and removing the insulation film by a wet etching process, wherein the wet etching process is conducted by an etchant to which both of the gate electrode and the compound semiconductor layer show a resistance.
申请公布号 US6586319(B1) 申请公布日期 2003.07.01
申请号 US19990307733 申请日期 1999.05.10
申请人 FUJITSU LIMITED 发明人 HIRANO HIDENORI
分类号 H01L29/73;H01L21/285;H01L21/308;H01L21/331;H01L21/335;H01L21/338;H01L29/205;H01L29/423;H01L29/737;H01L29/778;H01L29/812;(IPC1-7):H01L21/28;H01L21/44 主分类号 H01L29/73
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