发明名称 HARDWARE MECHANISM FOR IMPROVING PERFORMANCE IN MULTI- NODE COMPUTER SYSTEM
摘要 <p><P>PROBLEM TO BE SOLVED: To allow each switch to provide the routing of a data packet among a CPU node, an I/O node and a memory node in a dispersion-type multi-node computer system. <P>SOLUTION: Each switch is connected to a network interface controller (NIC) through the corresponding I/O node for data packet transfer on the network. Each NIC is mapped on the memory map. A part of a system address space forms a transmission window by each NIC connected to the corresponding switch. Each PIO writing does not depend on the writing on short notice to determine the destination of the transfer of the data packet. By using 'address aliasing', the CPU writing to the aliasized part of an NIC transmission window is directed to the NIC connected to the same switch as that of the CPU which did the write, at all times. <P>COPYRIGHT: (C)2003,JPO</p>
申请公布号 JP2003178043(A) 申请公布日期 2003.06.27
申请号 JP20020192022 申请日期 2002.07.01
申请人 FUJITSU LTD 发明人 FARRELL JEREMY J;MASUYAMA KAZUNORI;MIRYALA SUDHEER;PATRICK N CONWAY
分类号 G06F15/167;H04L12/56;H04L29/06;(IPC1-7):G06F15/177 主分类号 G06F15/167
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