| 摘要 |
PROBLEM TO BE SOLVED: To prevent break of a gate insulating film or etching remains, in patterning of a gate electrode of a dual-gate structure. SOLUTION: A trench-element isolation region 2 which partitions of an n-type semiconductor region 1n and a p-type semiconductor region 1p is formed on a semiconductor substrate 1. Thereafter, ion implantation of boron (B) as a p-type impurity is carried out over the entire surface of a non-doped polysilicon film 4, and a p-type implantation layer 6 is formed in a non-doped polysilicon film 4. Thereafter, heat treatment is carried out in order to activate a p-type implantation layer 6, to form a p-type polysilicon film 4a. Thereafter, patterning is performed for the p-type polysilicon film 4a, and an n-type gate electrode 4b is formed on the active region of an n-type transistor forming region Trn, and a p-type gate electrode 4c is formed on an active region of a p-type transistor forming region Trp. COPYRIGHT: (C)2003,JPO
|
