发明名称 Semiconductor memory device
摘要 A spare address conversion circuit makes an address assignment to spare sub word lines different from the address assignment to normal sub word lines between a mode of data writing and a mode of data reading. Data are written such that opposite data patterns are stored in spare word lines before and after address conversion. When a multi-selection occurs, there is data collision on the corresponding bit lines, so that the multi-selection can be detected without fail.
申请公布号 US2003117872(A1) 申请公布日期 2003.06.26
申请号 US20020269062 申请日期 2002.10.11
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 AKAMATSU HIROSHI
分类号 G01R31/28;G11C11/401;G11C29/00;G11C29/04;G11C29/24;(IPC1-7):G11C7/00 主分类号 G01R31/28
代理机构 代理人
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