| 摘要 |
Disclosed is a parallel distributed sample descrambling (DSS) apparatus and a method that lowers a clock speed of 622 MHz into 1/8 speed (77-76 MHz) and operates a serial descrambling processing in unit of bit by converting the processing into a parallel descarmbling processing in unit of byte, power consumption can thus be reduced and a sufficient timing margin can be secured. The parallel DSS apparatus includes a serial-parallel conversion unit for converting receiving data into parallel data (D[7:0]) and generating a counter signal, a header error check (hereinafter, as HEC) generation unit for generating HEC data of the receiving data by CRC calculation, and abstracting upper two bits of the HEC data, and a descarmbling processing unit for performing parallel descrambling of byte module by receiving output signals of the serial-parallel conversion unit and the HEC generation unit.
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