| 摘要 |
PURPOSE: A method for forming a via hole in a semiconductor device is provided to be capable of restraining generation of metallic polymers due to over-etch and forming uniform via hole irrespective of the thickness difference of an oxide layer. CONSTITUTION: An interlayer dielectric(12) having a contact hole is formed on a silicon substrate(10). An adhesive layer(14) is formed at inner walls of the contact hole and a tungsten plug(16) is formed in the contact hole. A metal wiring(18) and an anti-reflective layer(20) are sequentially formed on the resultant structure. An oxide layer(22) having low dielectric constant and a planarized insulating layer(24) are sequentially formed on the resultant structure. A via hole(26) is formed to expose the metal wiring by sequentially etching the planarized insulating layer(24) and the oxide layer(22) using plasma dry etching. At this time, mixed gases of CxFy, O2 and Ar added in N2 gas are used as an activation gas.
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