| 摘要 |
PURPOSE: A clock signal phase control circuit device and a clock signal phase control method are provided to improve the reliability of the synchronous signal outputted from the buffer simultaneously without the distortion by implementing the time control block capable of controlling the phase of the frequency to generate at the oscillator so as to remove the problem generated at the high speed substrate. CONSTITUTION: A clock signal phase control circuit device includes an oscillator(12) for outputting the frequency to generate the synchronous signal, at least one buffers(B1,B2,B3) for outputting the synchronous signal by inputting the frequency outputted from the oscillator(12) into the clock signal and a pair of time control blocks(T2,T3). The time control blocks(T2,T3), connected between the output terminal and the input terminal of the buffers(B1,B2,B3), controls the phase of the clock signal inputted to the buffers(B1,B2,B3).
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