Data pre-reading and error correction circuit for a memory device

摘要

A circuit for correction of errors in a memory device comprises a data word byte counter 16, data encoders 18 and 20, a syndrome accumulator 22, a data word byte address generator 24, a comparator 26, a decoder 28 and an error correction enable buffer 30. The error correction circuit 4 is coupled to a memory array 2 through a pre-read input-output bus 14, and is further coupled to an input-output multiplexer buffer 6 which is coupled between the memory array 2 and a data bus 12.