发明名称 SEMICONDUCTOR DEVICE, METHOD FOR DESIGNING THE SAME PROGRAM AND APPARATUS THEREOF
摘要 PROBLEM TO BE SOLVED: To reduce the time required for the design by eliminating failures without generating new failure spots when failure spots are detected between a lattice-like power supply wiring and an inter-cell signal wiring. SOLUTION: Functional blocks are disposed (S1), the lattice-like power supply wirings for supplying a power supply potentials to the functional blocks are disposed (S2), cells for constructing the functional blocks are disposed (S3), an inter-cell wiring is established (S4), and it is determined whether a cell terminal is not shorted to the power supply wiring, and whether the spacing between the inter-cell wiring and the power supply wiring satisfies a design rules (S5). When a failure is determined at the step S5, region A including the failure spot is further specified (S7), the power supply wiring is shifted in the direction at right angles to the longitudinal direction of the wiring in the region A, and the process returns to step S5 (S8). The power supply wiring in the region A is connected to a power supply wiring at the same potential in the other layer and in crossover relation therewith via an interlayer contact. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003174089(A) 申请公布日期 2003.06.20
申请号 JP20010373517 申请日期 2001.12.07
申请人 FUJITSU LTD 发明人 SHIBAMOTO WATARU
分类号 G06F17/50;H01L21/3205;H01L21/82;H01L23/52;(IPC1-7):H01L21/82;H01L21/320 主分类号 G06F17/50
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