发明名称 |
Verfahren und Vorrichtung zur Befehlsausgabe |
摘要 |
An instruction selector receives M instructions per clock cycle and stores N instructions in an instruction queue memory. An instruction queue generates a precedence matrix indicative of the age of the N instructions. A dependency checker determines the available registers for executing the instructions ready for execution. An oldest-instruction selector selects the M oldest instructions responsive to the precedence matrix and the eligible queue entry signals. The instruction queue provides the M selected instructions to execution units for execution. Upon completing the instructions, the execution units provide register availability signals to the dependency checker to release the registers used for the instructions. <IMAGE> |
申请公布号 |
DE69624159(T2) |
申请公布日期 |
2003.06.18 |
申请号 |
DE1996624159T |
申请日期 |
1996.03.01 |
申请人 |
FUJITSU LTD., KAWASAKI |
发明人 |
SHEBANOW, MICHAEL C.;GMUENDER, JOHN;SIMONE, MICHAEL A.;SZETO, JOHN R.F.S;MARUYAMA,;TOVEY, DEFOREST W. |
分类号 |
G06F9/38;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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