| 摘要 |
A hole filling process for an integral circuit in which a hole (10) connected between two wiring levels in the integrated circuit are connected by a narrow hole, especially where the underlying level (18) is silicon. First, a physical vapor deposition (PVD) process fills a barrier tri-layer into the hole. The barrier tri-layer (26) includes sequential layers of Ti (20), TiN (22), and graded TINX (24) grown under conditions of a high-density plasma. Thereafter, a first aluminum layer (70) is PVD deposited under conditions of a high-density plasma. A filling aluminum layer (72) is then deposited by standard PVD techniques. <IMAGE> |
