发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To restrain a hold error upon performing a scan test in which a scan chain is formed by a plurality of flip-flops in a semiconductor integrated circuit. SOLUTION: The substrate potential of a transistor (an object transistor) in a part including one of a scan data input circuit part 601 in an area 10 of a scan type flip-flop circuit, a part outside the part for conducting high impedance control by a clock series signal in a master part 604S and a slave part 605S, and a data output buffer part 606 is separated from the source potential of the transistor and the source and substrate potential of non-object transistor other than the above transistor. During normal operation, the substrate potential of the object transistor is made at the same as the substrate potential of the non-object transistor to use the transistor, and in performing the scan test, for the substrate potential of the object transistor, back bias is applied to the side of raising the threshold of the transistor to perform the test. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003167030(A) 申请公布日期 2003.06.13
申请号 JP20010365586 申请日期 2001.11.30
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ISHIKURA SATOSHI;TANIGUCHI HIROKI
分类号 G01R31/28;H03K3/037;H03K19/00;(IPC1-7):G01R31/28 主分类号 G01R31/28
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