发明名称 |
Semiconductor memory circuit hard to cause soft error |
摘要 |
A memory cell of SRAM includes: two N-channel MOS transistors connected in series between a first storage node and a line of a ground potential and two N-channel MOS transistors connected in series between a second storage node and a line of a ground potential. Since no storage data is inverted unless one alpha-particle passes through two N-channel MOS transistors, a soft error hard to occur.
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申请公布号 |
US2003107913(A1) |
申请公布日期 |
2003.06.12 |
申请号 |
US20020238618 |
申请日期 |
2002.09.11 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
NII KOJI |
分类号 |
G11C11/41;G11C11/412;H01L21/8244;H01L27/11;H03K3/356;(IPC1-7):G11C11/00 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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