发明名称 CLOCK SWITCHING CIRCUIT AND NODE DEVICE
摘要 A clock switching circuit which is fed with clock signals corresponding to respective elements of a redundant system and outputs a clock signal corresponding to the system in operation while relaxing the phase fluctuation in response to a change in the system construction and a node device which is provided with the clock switching circuit. Useless accumulation of phase error is prevented with neither a drastic change in the construction nor a degradation of performance. Therefore, the clock switching circuit is constructed such that the phase of a synchronous clock signal synchronized with a clock signal corresponding to an element used antecedently is stepwise varied alternately in opposite directions each time the element being used is updated.
申请公布号 WO03049356(A1) 申请公布日期 2003.06.12
申请号 WO2001JP10513 申请日期 2001.11.30
申请人 FUJITSU LIMITED;UMEDA, NOBUYUKI;HATA, AKIHIRO;SATO, HIROYUKI;TSUJI, HIDEO;SUMINO, SATOSHI 发明人 UMEDA, NOBUYUKI;HATA, AKIHIRO;SATO, HIROYUKI;TSUJI, HIDEO;SUMINO, SATOSHI
分类号 H04J3/06;(IPC1-7):H04L7/04;H04L7/00 主分类号 H04J3/06
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