发明名称 |
Semiconductor memory device having memory cells each capable of storing three or more values |
摘要 |
Memory cells are used which each have a MOSFET that holds an information voltage of three or more values at its gate, a writing transistor that supplies the information voltage of three or more values to the gate of the MOSFET, and a reading transistor connected in series with the MOSFET. A plurality of reference voltages corresponding to the information voltage of three or more values are applied from a source line to the sources of the MOSFETs, so that digital data is produced by a combination of on-state/off-state of the MOSFET and the plurality of reference voltages or that the source voltages themselves of the MOSFETs are produced as read voltages.
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申请公布号 |
US6577530(B2) |
申请公布日期 |
2003.06.10 |
申请号 |
US20010982162 |
申请日期 |
2001.10.19 |
申请人 |
HITACHI, LTD. |
发明人 |
MURANAKA MASAYA;ITO YUTAKA |
分类号 |
G11C11/401;G11C11/405;G11C11/56;G11C16/04;H01L21/8242;H01L27/105;H01L27/108;H01L27/115;H01L27/12;(IPC1-7):G11C11/40 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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