| 摘要 |
PURPOSE: An ATM multiplexing/demultiplexig apparatus in an IMT-2000 system is provided to design a BSC and a BTS interface board by implementing a logic which connects an upper ATM device by UTOPIA level 1 standard and various physical devices by UTOPIA level 2. CONSTITUTION: An egress receiver(10) receives cells from an upper ATM device by UTOPIA level 1 and stores them in DPRAMs(Dual Port RAM) of 16 ports divided with reference to a GFC(Generic Flow Control) field of an ATM cell header. An egress cell controller(20) counts cells stored in each DPRAM of the ports, and outputs ext_cell_rdy to an egress transmitter if a cell count for each port is not '0', or outputs erx_cell_rdy to the egress transmitter(10) if the cell count is not '2'. An egress DPRAM(30) stores cells for the 16 ports and stores two cells for each port. An egress transmitter(40) performs UTOPIA level 2 master interfacing with multi-physical devices, and transfers a cell to a pertinent port when a signal that there is a cell in each DPRAM port is received from the egress cell controller(20) and an available signal is transmitted to a corresponding access. An ingress receiver(50) performs UTOPIA level 2 master interfacing with the multi-physical devices, and receives a cell from a pertinent port when a signal that a cell can be received by an internal FIFO unit is received from an ingress cell controller and a cell available signal is transmitted to a corresponding address. An Internet FIFO unit(70) receives a write enable signal from the ingress receiver(50) and stores data coming from lower multi-physical devices. An ingress cell controller(60) counts cells stored in the FIFO unit(70), and outputs itx_cell_rdy to an ingress transmitter if the cell count is not '0' or outputs irx_cell_rdy to the ingress receiver(50) if the cell count is not '4'. An ingress transmitter(80) reads a cell from the FIFO unit and transfers the cell to an upper ATM device by UTOPIA level 1.
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