| 摘要 |
PROBLEM TO BE SOLVED: To facilitate a DMA transfer operation at the time that the DMA transfer operation of a DMA transfer channel frequently arises by arbitrating the DMA and a CPU memory access via a DMA transfer system and compensating a memory access of the DMA without causing a failure of a system. SOLUTION: When a successive counter value of a memory access cycle (normal DMA cycle) other than a CPU memory access cycle via the DMA transfer system becomes a set value, a priority of a CPU memory access request via the DMA transfer system is lowered or the request is masked. Then, the mask is released when a normal DMA transfer request disappears. COPYRIGHT: (C)2003,JPO
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