| 摘要 |
A signal CLK is input to delay this by one unit-time by a delay circuit 11, and to output it as a reference signal REF via a multiplexer 13. Also, the signal CLK is input into a multiplexer 14, and into a delay circuit 12, and the signal delayed by two unit-times is also input into the multiplexer 14. In the multiplexer 14, in the event that data DIN is "0", the signal CLK is selected, and is output as transmission data DATA. On the other hand, when the data DIN is "1", the signal CLK delayed by two unit-times by the delay circuit 12 is selected, and is output as the transmission data DATA. A phase comparator 21 detects a phase difference between the transmission data DATA and the reference signal REF, and in the event that the phase of the transmission data DATA is ahead of that of the reference signal REF, outputs a phase-lead detection signal R having a pulse width of the phase difference amount. Also, in the event that the phase of the transmission data DATA is behind of that of the reference signal REF, it outputs a phase lag detection signal S having a pulse width of the phase difference amount. An RS latch 22 takes DOUT as "1" when the phase lag detection signal S is applied to the set input, and takes DOUT as "0" when the phase lead detection signal R is applied to the reset input.
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