发明名称 Nichtflüchtiger Halbleiterspeicher und diesen verwendendes Speichersystem
摘要 The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines (BL) basing upon a change, after the pre-charge, of the potential at each bit line (BL), without changing the column address. Even if a write bit error occurs, no write error is issued so long as the number of bits can be relieved by an ECC circuit.
申请公布号 DE69233028(D1) 申请公布日期 2003.06.05
申请号 DE1992633028 申请日期 1992.12.21
申请人 KABUSHIKI KAISHA TOSHIBA, KAWASAKI 发明人 TANAKA, TOMOHARU;MOMODOMI, MASAKI;KATO, HIDEO;NAKAI, HIROTO;TANAKA, YOSHIYUKI;SHIROTA, RIICHIRO;ARITOME, SEIICHI;ITOH, YASUO;IWATA, YOSHIHISA;NAKAMURA, HIROSHI;ODAIRA, HIDEKO;OKAMOTO, YUTAKA;ASANO, MASAMICHI;TOKUSHIGE, KAORU
分类号 G06F11/10;G11C16/10;G11C16/12;G11C16/24;G11C16/34;G11C29/00;G11C29/34;G11C29/52;(IPC1-7):G11C29/00;G11C16/06 主分类号 G06F11/10
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