发明名称 |
Reduced potential generation circuit operable at low power-supply potential |
摘要 |
A power supply circuit includes a first NMOS-type current mirror circuit which compares a first potential with a second potential, a second NMOS-type current mirror circuit which compares the first potential with a third potential, and a potential setting circuit which adjusts the first potential in response to outputs of the first and second NMOS-type current mirror circuits, such that the first potential falls between the second potential and the third potential. <IMAGE>
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申请公布号 |
EP1316871(A2) |
申请公布日期 |
2003.06.04 |
申请号 |
EP20020023520 |
申请日期 |
2002.10.22 |
申请人 |
FUJITSU LIMITED |
发明人 |
MORI, KATSUHIRO;FUJIOKA, SHINYA;OHNO, JUN |
分类号 |
G11C11/407;G05F3/26;H01L21/822;H01L27/04;H03K19/00;(IPC1-7):G05F3/26 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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