| 摘要 |
A ferro-electric memory device system and method is described for accessing and sensing memory cells of an FeRAM memory array with an open bit line architecture. The memory device permits the sharing of certain memory circuits such as, a sense amplifier, a data buffer, and a dummy cell between several segments of an array of FeRAM memory cells associated with a pair of bitlines of the array. Various combinations of segmented bit lines and/or segmented word lines facilitate sharing the memory circuits of the device between the array segments or multiple arrays of memory cells.
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